(1) Field of the Invention
The invention relates generally to non-volatile memory devices. More particularly, this invention relates to a magnetic random access memory (MRAM) device. Even more particularly, this invention relates to a configurable MRAM device having novel device architecture and novel methods for configuration.
(2) Description of the Prior Art
Magnetic memory devices are known in the art as a magnetic-based alternative to electrical-based memories. Magnetic memories are typically constructed from ferromagnetic materials. The particular type of magnetic memories described herein rely on magnetic polarization of ferromagnetic layers to store binary data states (0 and 1) and rely on tunnel-magneto-resistance (TMR) effects to read out these stored states. Referring now to FIG. 1, an exemplary magnetic memory cell 10 is shown in schematic form for two polarity cases. The magnetic memory cell 10 comprises two ferromagnetic layers 12 and 16. One ferromagnetic layer 12 comprises soft magnetic material, while the other ferromagnetic layer 16 comprises a hard magnetic material. The soft magnetic layer 12 and the hard magnetic layer 16 are each capable of holding a magnetic polarization as is shown by the directional arrow on each layer in the schematic. The magnetic polarization of the soft layer 12 can be altered by exposure to magnetic fields generated within the memory during normal operation. However, the magnetic polarization of the hard layer 16 cannot be altered after manufacturing. The hard layer 16 is therefore called a pinned layer 16 while the soft layer is called a free layer 12.
The pinned layer 16 and the free layer 12 are separated by a dielectric layer 14. Therefore, any current flow between the free layer 12 and pinned layer 16 must traverse the dielectric layer 14 by tunneling through the dielectric 14. It is known in the art that a relationship exists between the magnetic polar orientation of the free layer 12 with respect to the pinned layer 16 and the effective resistance of the memory stack 10. If as shown in the upper illustration, the free layer 12 is oriented in a polarity opposite that of the pinned layer 16, then a current source IC will generate a first voltage drop VC′. If the polarity of the free layer 12 is then reversed, as shown in the lower illustration, then the same current source IC will generate a second voltage drop VC″ that is a different value than the first voltage drop. It is further known that the second voltage drop VC″ will be substantially less than the first voltage drop VC′. Alternatively, the effective resistance of the device 10 is higher when the free layer 12 and pinned layer 16 have opposite orientations and is lower when the orientations are the same. This phenomenon is called a tunnel-magneto-resistance (TMR) effect. The device 10 is typically called a magnetic tunnel junction (MTJ). The TMR effect can be used to distinguish between two physical states of the MTJ device such that binary data can be stored and read. Therefore, the MTJ device 10 is called a MTJ memory cell, a magneto-resistive cell, or simply a magnetic memory cell.
Referring now to FIG. 2, the exemplary magnetic memory cell 10 is shown in a simplified isometric illustration. In a typical application, many thousands or millions of memory cells 10 are formed in two or three dimensional arrays. In a typical array, the memory cells 10 are formed at the crossing points of perpendicular conductive lines in the memory array. In the illustrated example, a conductive word line WL 24 is formed under the magnetic memory cell 10 and a conductive bit line BL 20 is formed over the cell 10. For reasons that will be explained below, the bit line BL 20 electrically contacts the cell 10. As described above, the magnetic polarity of the free layer of the cell 10 can be altered by magnetic fields produced within the memory array. More particularly, the magnetic array produces magnetic fields capable of flipping the polarity of the free layer between same polarity and opposite polarity states with respect to the pinned layer. Typically, the memory array utilizes the word line WL 24 and bit line BL 20 conductors to generate localized magnetic fields HWL and HBL.
When an electrical current travels through any conductor, a magnetic field is generated by the movement of the electrical charges. This magnetic field forms as continuous field lines that surround the conductor and that are perpendicular to the direction of current flow. In addition, the orbital direction of the magnetic field lines (clockwise, counterclockwise) depends on the direction of the current flow in the conductor. Finally, the magnitude of the magnetic field is proportional to the current value in the conductor. In the exemplary case, current IBL flows in the bit line BL 20 and generates a bit line magnetic field HBL. Likewise, current IWL flows in the word line WL 24 and generates a word line magnetic field HWL. As can be seen, the bit line and word line magnetic field lines that surround the conductors will intersect the memory cell 10 and these intersections will occur from different directions. It is known in the art that the interaction of the bit line field HBL and the word line field HWL can be advantageously used to selectively magnetize the free layer of the cell 10 to a particular orientation while not disturbing the state of any other cells. To accomplish this, the word line and bit line currents IWL and IBL are kept low enough such that the magnetic fields HWL and HBL generated from the selected word line WL 24 and bit line BL 20 are not sufficient, by themselves, to change the free layer orientation of any cells 10. However, when the magnetic fields HWL and HBL combine at an intersection, as in the example, then the selected cell 10 will be programmed.
Referring now to FIG. 3, a schematic illustrates an exemplary programming technique used in many magnetic memory arrays. In this section of the array, several memory cells C1, C2, and C3 are connected to a common bit line BL1. Each cell has a separate word line WL1, WL2, and WL3. In addition, each cell has a separate selection transistor 44, 46, and 48 coupled between the cell and ground. In this example, memory cell C2 is selectively programmed by conducting current IBL1 through the bit line BL1 and by conducting current IWL through the word line WL2. A fixed current direction is used for the word line current IWL. However, the direction of the bit line current IBL1 is determined by the data value (0 or 1) that is to be written into the cell. In the schematic, switches SW1 and SW2 allow the bit line programming current IPROG1 to flow from left to right to ground. The combination of the magnetic fields from the bit line and word line currents IBL1 and IWL is sufficient to program the free layer of the selected cell C2 to a first binary state of, for example, an opposite magnetic orientation to that of the pinned layer. If switches SW1 and SW2 are set to allow the programming current IPROG2 to flow from right to left, then the cell C2 is programmed to the second binary state of, for example, the same magnetic orientation as the pinned layer.
Care must be taken in the above-described programming method to insure that the bit line and word line currents IBL1 and IWL are sufficient, in combination, to generate optimal magnetic fields to program the selected cell while not disturbing unselected cells. Insufficient programming current may result in slow or unreliable programming. Alternatively, excessive programming current may result in uncontrolled re-programming of non-selected cells. To achieve optimal performance, a proper balance between bit line and word line programming currents IBL1 and IWL must be established. As an addition consideration, the relative timing of the bit line and word line currents IBL1 and IWL is critical to achieving a necessary combined magnetic field vector for the required time to program the selected cell. Minimal IBL1 and IWL current overlap is desired to achieve high speed operation with minimal power consumption. However, inadequate current overlap may result in unreliable programming. Achievement of optimal performance over a large number of manufactured memory arrays is difficult due to lot-to-lot or even device-to-device variation in processing parameters.
Referring now to FIG. 4, an exemplary cell reading technique for a magnetic memory array is illustrated for the exemplary array section. During a reading operation, switch SW1 is set to allow reading current IREAD to be conducted through the bit line BL1. To select a cell for reading, its selection transistor is turned ON. In the schematic, the selection transistor 44 is turned ON to provide a low resistance path from one layer of cell C1 to ground. The bit line current IBL1 is thereby conducted from the bit line BL1, through cell C1 and transistor 44, and into ground. As a result, current flowing through the cell C1 exhibits the tunnel-magneto-resistance (TMR) effect such that the resulting voltage drop across the cell C1 varies depending on the relative magnetic orientation of the free and pinned layers. Switch SW2 is set to present the bit line BL1 voltage, comprising substantially the selected cell C1 voltage drop, to a sense amplifier, or comparator, 50. The bit line BL1 voltage VBL1 is compared to a reference level REF. If the bit line voltage VBL1 is greater than REF then the read-out state DOUT of the cell C1 is one of the binary values (such as logic “0”). If the bit line voltage VBL1 is less than REF then the read-out state DOUT of the cell C1 is another of the binary values (such as logic “1”).
Care must be taken in the above-described reading method to insure that the reading current IREAD is sufficient to generate an optimal voltage drop across the selected cell. Insufficient reading current may result in cell voltage drops that are too small to provide a sufficient difference between opposite and same orientation cells. This circumstance may result in unreliable reading and slow operation. Alternatively, excessive reading current may result in excessive power consumption in the memory device or even generate excessive magnetic fields near the bit lines such that uncontrolled programming occurs. As an addition consideration, the relative timing between the bit line current IBL1 and digital sampling of the sensing amplifier 50 output DOUT is critical to achieving reliable, high speed operation. As stated above, achievement of optimal performance over a large number of manufactured memory arrays is difficult due to lot-to-lot or even device-to-device variation in processing parameters.
Several prior art inventions relate to MRAM device architectures and to non-volatile memory configuration. U.S. Pat. No. 6,421,271 to Gogl et al describes a MRAM (magneto-resistive random access memory) architecture in which a single switching transistor is allocated to a plurality of TMR (tunnel magneto-resistive) memory cells. Space requirements for the resulting MRAM array are thereby reduced. U.S. Pat. No. 6,473,335 to Bohm et al is describes a MRAM architecture in which single line driver circuits are assigned via connecting nodes to two memory cell arrays to reduce the space requirements for driver circuits in the overall array.
U.S. Pat. No. 6,487,108 to Pochmuller describes a MRAM architecture in which a plurality of memory cell blocks are supplied with differing operating voltages to optimize use of the available voltage headroom. U.S. Pat. No. 6,577,527 to Freitag et al describes a MRAM device in which compensating currents are provided in the bit lines of unselected cells near a selected cell to counteract stray magnetic field and to thereby prevent undesired programming of the unselected cells. U.S. Pat. No. 6,781,896 to Lammers et al describes a MRAM architecture having redundant cells. Main cells arrays and redundant arrays are provided in a plurality of planes or in other configurations on the same chip.
U.S. Pat. No. 6,791,871 to Freitag et al describes a MRAM array architecture where each unit comprises a selection transistor and a MTJ (magnetic tunnel junction) cell connected in parallel. U.S. Pat. No. 6,462,985 to Hosono et al describes a non-volatile semiconductor memory device with an initial setting function. Initial setting data is held in the non-volatile memory (EEPROM) and is read out during power-up. The initial setting data may include defective array address, control data for programming and erasing, and chip identification codes.